1. Field of the Invention
The present invention relates to an integrated common source power MOSFET device and to the manufacturing process thereof.
2. Discussion of the Related Art
As is known, power MOSFET devices are typically of a vertical current type, wherein the substrate forms the drain region, and the epitaxial layer accommodates a plurality of body regions arranged side by side, which in turn accommodate source regions. The body and source regions are shorted by a metallization. Gate regions are arranged, insulated, on the body of semiconductor material, generally between adjacent pairs of body regions.
With the above type of structure, it is possible to obtain one or more common drain MOSFET devices.
However, in some applications, pairs of power MOS transistors are used having source terminals connected together and with independent drain and gate terminals so that they can be independently driven. An application having this requirement is, for example, synchronous rectification on the secondary winding of LLC resonant converters, as discussed in detail hereinafter.
As is known, resonant converters are a vast class of switching converters characterized by the presence of a resonant circuit that actively participates in determining the input-output power flow. In these converters, a bridge (half-bridge), made up of four (two) power switches (typically N-channel MOSFETs) and supplied by a d.c. voltage, generates a square wave voltage, which is supplied to a resonant circuit tuned at the fundamental frequency of the square wave. In this way, on account of its selective characteristics, the resonant circuit responds mainly to the fundamental component and negligibly to the higher order harmonics. As a result, the circulating power can be modulated by varying the frequency of the square wave, and, according to the configuration of the resonant circuit, the currents and/or the voltages associated with the power flow have a sinusoidal or piecewise sinusoidal pattern.
The above voltages and/or currents are rectified and filtered so as to supply d.c. power on the load. In network applications, for reasons of safety standards, the rectification and filtering system that supplies the load is coupled to the resonant circuit through a transformer that provides the insulation between source and load, as required by the aforesaid standards. As in all insulated network converters, also in this case the approach is to refer to a primary side (in so far as it is connected to the primary winding of the transformer) connected to the input source, and a secondary side (in so far as it is connected to the secondary winding or windings of the transformer), which supplies power to the load through the rectification and filtering system. FIG. 26 shows a high level block diagram of a resonant converter of the type described.
Among the many types of resonant converters that can be built on the basis of the general architecture of FIG. 26 and are classified on the basis of the configuration of the resonant circuit that they use, the so called LLC resonant converter is encountering large popularity, especially in its half-bridge version (illustrated in FIG. 27). The name (LLC resonant converter) stems from the fact that the resonant circuit uses two induction coils (Ls and Lp) and a capacitor (Cr). For convenience, from now on reference will be made to the half-bridge version alone, but it is clear that the following can be applied entirely also to the bridge configuration.
LLC resonant converters are characterized by high conversion efficiency (it is possible to reach easily an efficiency higher than 95%), capacity for working at high frequencies, low generation of electromagnetic interference (EMI) and, finally, high power density (i.e., the capacity of obtaining conversion systems of reduced volume), characteristics to which a particular emphasis is given in many present day applications.
Typical examples of these applications are AC-DC adapters used in high-range PC notebooks or in PC desktops with reduced aspect ratio, and supply systems for network servers and for telecommunications apparatuses.
Notwithstanding the advantages of LLC resonant converters, in these, as in traditional switching converters, the maximum efficiency that can be achieved may be limited by the losses in the secondary rectifiers, which, in LLC resonant converters, represent the vast majority of losses.
It is known that, in order to significantly reduce the losses linked to the secondary rectification, it is possible to resort to the so-called “synchronous rectification” technique, wherein the rectifier diodes D1, D2 are replaced by MOSFETs having appropriately low dynamic resistance RDS(on) so that the voltage drop across the transistors is significantly lower than the drop across the diodes (with consequent reduction in conduction losses). Obviously, the MOSFETs are driven so as to be functionally equivalent to diodes.
FIG. 28 illustrates an LLC resonant converter with secondary synchronous rectifiers (transistors SR1, SR2). As may be noted, the position of the transistors SR1, SR2 has been shifted with respect to that of the rectifier diodes D1, D2 in FIG. 27 in order to be able to drive the MOSFETs SR1, SR2 with respect to ground. From the functional standpoint, however, there is no difference.
At the current state of the art, integrated control circuits on the market are specifically dedicated to driving synchronous rectifiers for LLC resonant converters, i.e., designed to supply the signals GD1, GD2 indicated in FIG. 28. Normally, these signals are generated by processing other signals, among which the drain-to-source voltages of the MOSFETs SR1, SR2, as illustrated in the block diagram of FIG. 29. In order to reproduce operation of the rectifiers D1, D2 of FIG. 27, the MOSFETs SR1 and SR2 are to be driven in phase opposition so that the respective drains are able to move independently.
Experience shows that the parasitic resistances and inductances of the circuit metallizations that comprise the MOSFETs SR1, SR2 (including those linked to the package of the MOSFETs themselves), as well as those of the connections between the pins of the control device and the drain terminals of the transistors SR1 and SR2 are particularly critical for proper generation of the signals GD1, GD2 and, thus, for proper operation of the synchronous-rectification system and of the entire converter.
In order to reduce these critical aspects, it would thus be desirable to be able to integrate the two transistors SR1, SR2 in the same package. However, with the low-voltage technologies used to obtain the integrated control circuit, the bottom surface of the silicon die corresponds to ground so that, with a conventional embodiment of the MOSFETs, three separate dice are necessary in a package with three insulated frames in order not to electrically connect the drain terminals to one another and to ground.
Similar problems are encountered in general in all the cases where it is necessary to have an array of open-drain MOSFETs with grounded source, that can be driven independently of one another, to be accommodated in a single package.
In fact, with the typical structure of MOSFETs (which have the bottom surface of the die corresponding to the drain terminal), current solutions require the use of a number n of silicon dice equal to the number of the MOSFETs, each of which is assembled on an own copper island insulated from a metallic standpoint from all the others so as to enable the drain terminals to move independently of one another. The difficulties of mechanical formation of a frame with n islands, as well as the cost of assemblage of n dice are an evident limitation of this approach.
In general, the integration of power MOS transistors in different dice, connected together, causes a very high gate-drain parasitic capacitance that generates problems of dissipation, which are critical in the case of devices operating at rather high frequencies (in the case of the resonant converters described above of the order of megahertz) and at high currents (of the order of some amps).
U.S. Pat. No. 4,738,936 describes a manufacturing process of lateral MOSFETs using the Mesa technique, including digging in the semiconductor body to obtain the body region. This solution sets, however, limits of scaling-down of the structures and thus limits the possibility of achieving high levels of performance.